1. Field of the Invention
The invention relates to an integrated connection arrangement, and in particularly to semiconductor components having a substrate, an outer conductive structure remote from the substrate.
2. Description of the Related Art
An integrated circuit arrangement may include an outer conductive structure having a bonding pad with a bonding zone and a test zone. A metallization stratum having vias may be arranged between two metallization strata with interconnects. Current flows in the vias normal to or counter to a normal direction to a main area, but not parallel to the main area or transversely with respect to the normal direction.
Vias may have the following common features:                current flows in the normal direction or opposite to the normal direction to the main area, but not parallel to the main area,        arranged with a large part of their cross-sectional area of a cross section parallel to the main area or completely overlapping an underlying interconnect or an overlying interconnect, and        sections do not overlap an overlying or underlying interconnect (e.g., sections which are offset with respect to the interconnect) do not influence the function of the integrated circuit arrangement, (e.g., not utilized as an electrically conductive connection that is required for the function of the integrated circuit arrangement).        
The fabrication of metallization strata with interconnects and vias, on the one hand, and of metallization strata having exclusively vias, on the other hand, are customary and accepted techniques for producing integrated circuit arrangements. In terms of process engineering, vias of a metallization stratum may have common or similar dimensions. By contrast, interconnects of a metallization stratum have contours that deviate significantly from one another. The length may be a multiple of the width of an interconnect.
Criteria for a metallization layer have increased with advances in technology in the production of integrated circuit arrangements. For example, in bipolar and CMOS technologies, current densities of more than 1, 5 and even 10 milliamperes per square micrometer of bulk cross-sectional area are common. A metallization layer, such as a copper metallization layer, may have low bulk resistance, despite small dimensions for the metallization layer. Since copper surfaces may not be cost-effective or include a fabrication-proven mounting technique, aluminum may be used as a last metallization plane. Aluminum has a lower current-carrying capacity. An aluminum bonding pad may be loaded with lower absolute currents, and is less resistant to electro-migration than a copper structure having similar dimensions.
The bonding pad may have a significant influence on the life time of a final product. Current densities are increasing and smaller test and mounting bonding pads are desirable in light of rising integration density associated with additional functions. Accordingly, current densities per bonding pad will increase further.
Therefore there is a need for an improved connection arrangement having improved electrical properties.